Integrated circuit design processes have evolved quickly to keep pace with the rapid growth in integrated circuit (IC) complexity. Early IC devices, known as Small Scale Integration chips, had relatively few logic gates. Later, as IC technology advanced, it became possible to implement Medium Scale Integration chips with hundreds of logic gates. With the arrival of Large Scale Integration, thousands of logic gates could be implemented on a single chip.
As IC complexity increased, IC design became more complicated and increasing interest was shown in automated processes that could assist chip designers with design and implementation activities. Electronic Design Automation (EDA) tools were developed and these tools have continued to evolve with the arrival of Very Large Scale Integration (VLSI), which initially allowed single chips to carry hundreds of thousands of transistors.
Present EDA tools permit a chip designer to specify a chip in abstract, functional terms using a Hardware Description Language (HDL), translate the HDL design description into a gate-level description, layout the placement of gates and route connecting paths, and generate a mask for chip fabrication. Two examples of HDL include Verilogo.RTM. HDL, developed by Gateway Design Automation, and VHSIC HDL (VHDL), developed under contract from the U.S. Dept. of Defense.
Throughout the remainder of this disclosure, VHDL and especially Verilog HDL are discussed but no other description language is mentioned. It should be understood that many of the concepts discussed herein, particularly those of the present invention, are not limited to these two languages but instead are applicable to a wide range of languages.
Verilog HDL allows a designer to specify a chip in terms of modules that are described at any or all of four levels of abstraction: functional or algorithmic (behavioral-level), flow of data (dataflow-level), gates and interconnections (gate-level), or switches, storage nodes and connections between them (switch-level). The behavioral level is the most abstract level and is independent of device implementation details. The switch level is the least abstract and is very dependent on device implementation details. Modules are generally hierarchical, meaning that higher-level, more complex modules incorporate one or more lower-level, less complex modules. At some level, a module usually represents some component such as a storage register, a multiplexor or a UART (Universal Asynchronous Receiver/Transmitter).
A number of EDA tools for Verilog HDL and VHDL have automated a number of design steps including functional simulation and logic synthesis. Manual intervention is required, however, to manage the overall process, verify functional design, and ensure design requirements are achieved. Considerable manual effort is required to design chips that must meet stringent requirements such as high speed operation, small die size, wide temperature ranges, or low power requirements. Chips for microprocessors and random access memory (RAM) usually must be designed manually to achieve optimal performance because the automated tools are not yet good enough. This is particularly true for submicron technologies because layout decisions can dominate timing characteristics.
Further advances in VLSI technology permit fabrication of chips with millions of transistors. Circuits of such complexity can implement complete systems that formerly were implemented on a main board and one or more ancillary boards. So called System-on-a-chip (SOC) devices and other complex devices often integrate proprietary modules from different vendors that do not adhere to any particular interface standard; therefore, "oglue logic" or interface circuitry must be designed manually to interconnect these proprietary modules. The time and effort required to design and implement this glue logic increases the time and the cost required to design and implement a chip.